A Chaotic IP Watermarking in Physical Layout Level Based on FPGA
A new chaotic map based IP Acrylic Plant Marker (Intellectual Property) watermarking scheme at physical design level is presented.An encrypted watermark is embedded into the physical layout of a circuit by configuring LUT (Lookup Table) as specific functions when it is placed and routed onto the FPGA (Field-Programmable Gate Array).The main contrib